Semiconductor integrated circuits (ICs) are typically designed and fabricated by preparing a schematic diagram or hardware description language (HDL) specification of a logical circuit in which functional elements are interconnected to perform a particular logical function. The schematic diagram or HDL specification is synthesized into cells of a particular cell library. Each cell corresponds to a logical function unit, which is implemented by one or more transistors or other devices. A series of computer-aided design tools generate a netlist of the selected cells and the interconnections between the cells. The netlist is used by a floor-planner or placement tool to place the selected cells at particular locations in an integrated circuit layout pattern. The interconnections between the cells are then routed along predetermined routing layers. Once the selected cells have been placed and routed, the netlist, the cell layout definitions, the placement data and the routing data together form an integrated circuit layout definition, which is used to fabricate the integrated circuit.
During various stages of the design process, verification tools are used to verify different aspects of the design, such as the logic or analog function, the timing, and adherence to certain design rules. One measure of the performance of an IC is expressed by the time delays within the circuit, such as propagation delays, setup delays and hold delays. Propagation delays include the time required for a signal to travel from one location to another, such as from the input of a cell to the output of the cell. A setup delay is the time duration that a signal must be available at an input to a cell prior to a respective clock or other signal transition. A hold delay is the time duration that a signal must be stable after a respective clock or other signal transitions.
Further, a worst case setup violation refers to a violation that occurs at a cell input assuming that the signal path leading to that input has a worst case (maximum) delay over variations in process, voltage and temperature. A best case hold violation refers to a violation that occurs at a cell input assuming that the signal path leading to that input has a best case (minimum) delay over variations in process, voltage and temperature. Therefore, one variation of a hold violation may be perceived as when the signal arrives too early at the destination, resulting in errors or violations in the system.
Since setup violations traditionally have been more difficult to solve than hold violations, the adjustment and repair of best case hold violations within the design process are often ignored until after much of the functional verification and setup violations have been fixed. Therefore, designers often look for a minimal-effort approach.
However, fixing the hold violations in a design is a crucial phase in static timing analysis. The delays can be in the form of buffers or delay cells. In a design which has already gone through Physical Design (PD), the number of additional buffers and delay cells which are added to fix hold violations will have to be restricted to a minimum in order to reduce the PD and static timing iteration. Additional buffers/delay cells increase the power, area and effect of process variation. But at the same time, the hold violations will have to be fixed.
The conventional approach to resolving hold violations is to determine if enough setup margin exists to delay the data via inserting a buffer or cell at the input pin of the violating storage element, such as a flip-flop or a memory device. For example, if an endpoint with a hold violation has enough setup margin, the designer may insert a generic buffer at the endpoint (i.e. input pin to the flip-flop), thereby delaying the incoming signal relative to the clock input. However, if the setup margin does not allow for the addition of buffers/delay cells at the endpoint, then the timing path is traced back to find an appropriate insertion point. Further, if the hold violations cannot be fixed in a single timing path, then other timing paths are explored to correct the hold violations in the same manner noted above. Therefore, the conventional approach unnecessarily adds additional buffers and does not utilize a bottleneck-based analysis. Further, the conventional approach has a designer sorting through hundreds or even thousands of possible paths, in order to repair hold violations.
As a result, a need exists to minimize the number of buffer or delay cells used to fix hold violations. By reducing the number of hold buffers utilized in the design, the amount of power utilized by the design is less, the size of the design can be further reduced and the probability of process variations is reduced. It also helps in the placement and routing of highly congested designs. Furthermore, a need also exists for a method and/or apparatus that not only addresses the hold violations, but also does not degrade setup violations by verifying that enough setup margin is available.